Components - BUS
🧠 Mainboard & System Bus — How the CPU Communicates with Memory and Devices
A clear, developer‑friendly explanation of how the CPU uses the system bus to communicate with RAM and I/O devices.
🖥 What Is a Mainboard?
The mainboard (motherboard) is the central hub that connects:
- CPU
- RAM
- Storage
- GPU
- I/O devices
It allows the CPU to exchange data and control signals with the rest of the system.
⚙ What Is the System Bus?
The system bus is the communication highway between the CPU, memory, and peripherals.
It consists of three main buses:
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Address Bus → Where?
Data Bus → What?
Control Bus → When / How?
1️⃣ Address Bus — “Where to Access”
Role
The CPU uses the address bus to specify which memory location or device address to access.
Example
1
CPU → Request data from address 0x1000
Key Points
- Usually one‑way (CPU → Memory)
- Bus width determines maximum addressable memory
| Address Width | Max Address Space |
|---|---|
| 32‑bit | 4 GB |
| 64‑bit | Very large |
2️⃣ Data Bus — “What Data Moves”
Role
Transfers actual data between CPU, memory, and devices.
Example
1
Memory → CPU : Data = 0xA5F3
Key Points
- Two‑way communication
- Wider bus = higher data throughput
| Data Width | Data per Transfer |
|---|---|
| 32‑bit | 4 bytes |
| 64‑bit | 8 bytes |
3️⃣ Control Bus — “When and How”
Role
Controls timing, commands, and coordination between components.
Common Signals
- Read / Write
- Clock
- Interrupt
- Reset
- Bus Request / Grant
Example
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2
CPU → READ command
Memory → READY response
🔄 CPU Memory Read — Real Execution Flow
Step‑by‑Step
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2
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4
1. CPU puts target address on Address Bus
2. CPU asserts READ on Control Bus
3. Memory places data on Data Bus
4. CPU receives the data
Meaning
- Address Bus = selects target
- Control Bus = defines operation
- Data Bus = transfers data
🧩 Conceptual Diagram
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┌──────────┐
│ CPU │
└────┬─────┘
│
┌───────┴────────┐
│ System Bus │
├────────┬───────┤
Address Bus Data Bus Control Bus
│ │ │
RAM GPU I/O Devices
⚡ Why the System Bus Matters for CPU Performance
| Bus Type | Impacts |
|---|---|
| Address Bus | Maximum memory capacity |
| Data Bus | Memory bandwidth |
| Control Bus | Latency & synchronization |
A fast CPU cannot perform well if the bus becomes a bottleneck.
🧠 How Modern Systems Evolved Beyond a Single Bus
Then
- Single shared system bus
Now
- Integrated memory controllers
- Dedicated GPU bus (PCIe)
- High‑speed interconnects (UPI, Infinity Fabric, DMI)
- Point‑to‑Point communication architecture
The “system bus” concept now represents multiple specialized high‑speed links.
🎯 Developer Takeaways
✔ CPU performance depends on memory & bus throughput
✔ Data Bus width affects real bandwidth
✔ Address Bus limits memory capacity
✔ Control Bus ensures correct timing
✔ Modern systems replace shared buses with dedicated high‑speed links